1. Field of Invention
This invention is directed to a method of fabricating a high voltage PMOS device and more particularly to a method of fabricating a high voltage PMOS device having n-type source side doping in the manufacture of integrated circuits.
2. Description of Related Art
High voltage PMOS (HVPMOS) devices have a high breakdown voltage. There are two major challenges with HVPMOS devices. One is that the process window is not large enough. The overlay between the P-well and the active area must be at least 0.6 μm. Another challenge is in achieving a high enough breakdown voltage, for example, as much as 40 volts for a p-substrate wafer.
U.S. Pat. No. 5,578,855 to Gauffer et al describes a high voltage device having source and drain within an n-well and a p-field extension below the drain. U.S. Pat. No. 4,442,591 to Haken shows a high voltage device having both a source and a drain within a p-well and within an n-tank. U.S. Pat. No. 6,087,211 to Kalnitsky et al discloses a CMOS device having both low voltage and high voltage transistors. U.S. Pat. No. 5,650,658 to Beasom teaches tuning an n-well to form a drift region. There is an overlay between the n-well and p-well regions. U.S. Pat. No. 6,563,171 to Disney shows a high voltage PMOS device where everything in formed in an n-well. This patent also shows a high voltage NMOS device having the drain in an n-well and the source outside of the n-well. U.S. Pat. No. 6,063,674 to Yang discloses n-wells within p-wells. The source is in one n-well and the drain is in a second n-well. U.S. Pat. No. 5,698,457 to Noguchi shows a high voltage PMOS device having the drain in a p-well and the source in an n-well formed in the bottom surface of a p-well.